1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Related Art
Conventional technology is known for providing a gate trench portion in a mesa region, as shown in Non-Patent Document 1, for example. Furthermore, technology is known for, when implanting p-type impurities in a bottom portion of a valley between mesa regions, also implanting p-type impurities in the side portions of the mesa regions, as shown in Patent Document 1, for example.    Non-Patent Document 1: Tohru Oka et al., Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV, Jan. 28, 2014, Applied Physics Express, volume 7, 021002    Patent Document 1: Japanese Patent Application Publication No. 2012-178536
In order to improve the withstand voltage of a semiconductor device when the gate is OFF, it is preferable to provide a p+-type layer in contact with the side portions of the mesa regions provided in the gate trench portions and the bottom portion of the valleys between these mesa regions.